1. Field of the Invention
The present invention relates to a passivation film and a seal for an edge of a die which serve as a protective structure for a semiconductor device.
2. Description of the Background Art
In order to protect a region in which a circuit is formed (hereinafter, referred to as a xe2x80x9ccircuit regionxe2x80x9d) in a semiconductor device from influences of moisture and ions contained in an ambient air, a protective structure called a xe2x80x9cdie edge sealxe2x80x9d, xe2x80x9cguard ringxe2x80x9d or xe2x80x9cseal ringxe2x80x9d is provided on an inner side of a dicing line, that is, in the vicinity of an edge portion of a chip (die). A typical seal ring is formed of interconnect layers and contacts made of materials in the same manner as a circuit region in a semiconductor device, and surrounds the circuit region. Further, a protective film called a xe2x80x9cpassivation filmxe2x80x9d is provided on a surface of the semiconductor device to function to protect the surface of the semiconductor device, keeping the surface of the semiconductor device away from influences of an ambient air.
In recent days, a semiconductor device has been structurally further miniaturized, and an integration density as well as an operation speed thereof has been further increased. Under such a condition, higher importance has been placed on reduction of interconnect resistance. As a result, copper (Cu) having a relatively low resistance has been more frequently utilized as a material for interconnects. Accordingly, copper has been utilized also to form the above-mentioned seal ring in more instances.
FIG. 29 is a view illustrating a structure of a conventional semiconductor device, more particularly, is an enlarged view of an area of the conventional semiconductor device in which a seal ring is formed. As described above, a seal ring is typically formed on an inner side of a dicing line. The area illustrated in FIG. 29 includes a circuit region on the left-hand side of the drawing and includes a dicing region (a region to be cut during dicing) on the right-hand side of the drawing. It is noted that circuit elements of the semiconductor device are omitted in FIG. 29.
Referring to FIG. 29, a seal ring 110 includes a first contact 111, a first interconnect layer 112, a second contact 113 and a second interconnect layer 114. On a silicon substrate 101 having an isolation film 102 formed therein, an interlayer insulating film 103 having the first contact 111 formed therein, an interlayer insulating film 105 having the first interconnect layer 112 made of copper formed therein, an interlayer insulating film 107 having the second contact 113 formed therein and an interlayer insulating film 109 having the second interconnect layer 114 made of copper formed therein are formed. Further, etch stop layers 104, 106 and 108 are formed between the interlayer insulating films 103 and 105, the interlayer insulating films 105 and 107, and the interlayer insulating films 107 and 109, respectively.
Each of the first and second contacts 111 and 113 is made of tungsten (W), for example, while each of the interlayer insulating films 103, 105, 107 and 109 is made of plasma oxide, for example. Each of the etch stop layers 104, 106 and 108 is made of plasma nitride, for example.
Moreover, a passivation film 120 is formed on the uppermost interlayer insulating film. In an instance illustrated in FIG. 29, the passivation film 120 has a bilayer structure composed of a layer of plasma nitride (plasma nitride layer) 121 and a polyimide layer 122.
Because of provision of the seal ring 110 and the passivation film 120, the circuit region of the semiconductor device is protected from influences of moisture and ions contained in an ambient air, which makes it possible to ensure stability of properties of the semiconductor device over a long period of time.
Also, the seal ring 110 produces a further effect of preventing a crack from occurring in the circuit region at a time of cutting the dicing region during dicing. A crack which possibly occurs in the dicing region during dicing is prevented from propagating from the dicing region to the circuit region, because of provision of the seal ring 110 between the dicing region and the circuit region.
In the conventional semiconductor device, the passivation film 120 is formed only on one side of the seal ring 110 where the circuit region is provided (a circuit region side). Accordingly, on the other side where the dicing region is provided (a dicing region side), a top face of the interlayer insulating film 109 is exposed. Such configuration is employed in the conventional semiconductor device for the following reasons. If the passivation film 120 is formed on an entire surface of a wafer including the dicing region, a stress (or a crack) occurring in the dicing region due to a process of cutting the dicing region during dicing can easily propagate through the passivation film 120 to the circuit region, so that a crack is more likely to occur in the circuit region.
For the foregoing reasons, the conventional semiconductor device employs a configuration in which a top face of the uppermost layer of the seal ring 110, i.e., the second interconnect layer 114, is exposed as illustrated in FIG. 29. Accordingly, the top face of the second interconnect layer 114 is exposed to an ambient air in the conventional semiconductor device. When the uppermost layer of the seal ring 110, i.e., the second interconnect layer 114, is made of copper as in the instance of FIG. 29, the foregoing conventional configuration disadvantageously results in oxidation and corrosion of the second interconnect layer 114 because copper is more easily to be oxidized and corroded than other kinds of metal as a material for interconnects (such as aluminum). This invites reduction of the effect of protecting the semiconductor device which is achieved by the seal ring 110.
It is an object of the present invention to provide a semiconductor device capable of preventing a crack from occurring in a circuit region during dicing, while preventing a seal ring from being oxidized and corroded.
According to a first aspect of the present invention, a semiconductor device includes a seal ring and a passivation film. The seal ring is formed in an interlayer insulating film in the vicinity of an edge portion of a semiconductor chip, and surrounds a circuit region of the semiconductor chip. The passivation film is formed above the seal ring so as to cover a surface of the semiconductor chip, and has a first opening reaching a top face of the interlayer insulating film. Further, a top face of an uppermost layer of the seal ring is covered with the passivation film.
The top face of the uppermost layer of the seal ring portion is not exposed to an ambient air. Accordingly, even if copper, for example, is employed as a material for the uppermost layer of the seal ring, it is possible to prevent an effect of protecting the semiconductor device achieved by the seal ring from being reduced due to oxidation and corrosion of the uppermost layer. Further, because of provision of a region not including the passivation film, a stress generated at a time of cutting a dicing region during dicing can not easily propagate to a portion of the passivation film which is present on a circuit region. Hence, it is possible to prevent a crack from occurring in the circuit region.
According to a second aspect of the present invention, a semiconductor device includes a seal ring, an aluminum interconnect layer and a passivation film. The seal ring is formed in an interlayer insulating film in the vicinity of an edge portion of a semiconductor chip, and surrounds a circuit region of the semiconductor chip. The aluminum interconnect layer is formed on the seal ring. The passivation film is formed above the seal ring so as to cover a surface of the semiconductor chip, and has a first opening reaching a top face of the interlayer insulating film. Further, a top face of an uppermost layer of the seal ring is covered with the aluminum interconnect layer.
The top face of the uppermost layer of the seal ring is not exposed to an ambient air. Also, even if the aluminum interconnect layer is exposed in a region not including the passivation film, it is still possible to prevent reduction of the effect of protecting the semiconductor device achieved by the seal ring because aluminum is relatively resistant to oxidation and corrosion. Thus, the structure of the semiconductor device according to the second aspect of the present invention is effective in a situation where a high alignment accuracy can not be ensured or another situation where a space for forming a region not including the passivation film can not be obtained between a dicing region and the seal ring.
According to a third aspect of the present invention, a semiconductor device includes a seal ring, a first passivation film, an aluminum interconnect layer and a second passivation film. The seal ring is formed in the vicinity of an edge portion of a semiconductor chip so as to surround a circuit region of the semiconductor chip. The first passivation film is formed above the seal ring so as to cover a surface of the semiconductor chip, and has a first opening reaching a top face of an uppermost layer of the seal ring. The aluminum interconnect layer is formed in the first opening. The second passivation film is formed so as to cover the first passivation film and the aluminum interconnect layer, and has an etch selectivity relative to the first passivation film. Further, the second passivation film has a second opening reaching a top face of the first passivation film.
Since the aluminum interconnect layer is formed in the first opening of the first passivation film, the top face of the uppermost layer of the seal ring is not exposed to an ambient air. Also, even if the second opening is formed above the uppermost layer of the seal ring, the uppermost layer of the seal ring is not exposed because of provision of the aluminum interconnect layer. Further, there is no need to form the aluminum interconnect layer so as to have a width larger than that of the uppermost layer of the seal ring, thereby to contribute to miniaturization of the device. Moreover, the second passivation film has the second opening by which the top face of the first passivation film is exposed. This does not allow a stress generated at a time of cutting a dicing region during dicing to easily propagate to a portion of the passivation film which is present on a circuit region. As a result, it is possible to prevent a crack from occurring in the circuit region.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.